Seminar Formal Verification


In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics. [Wikipedia]

We particularily consider the verification of software systems including their modelling on different levels of abstraction and the specification of properties that are to be verified. Typical approaches are, for example theorem proving, testing, model checking, runtime verification, static analysis and type checking. They rely on formal concepts such as (temporal) logic, automata- and game theory or process algebras. The major goal is an automatic comparisson of the (possibly abstract) model and a property specification.

SS 2015
Preliminary meeting (Vorbesprechung)
Tuesday 15:00-16:00 1.108 (Besprechungsraum ISP), Building 64 (not every week)

Preliminary meeting (Vorbesprechung)
Tuesday April 7, 2015 15:00-16:00 (1.108 (Besprechungsraum ISP), Building 64)

click to view Dates.